Silicon Labs /EFR32MG22C224F512IM40 /LDMA_S /CH4_CTRL

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Interpret as CH4_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TRANSFER)STRUCTTYPE 0 (STRUCTREQ)STRUCTREQ 0XFERCNT0 (BYTESWAP)BYTESWAP 0 (UNIT1)BLOCKSIZE 0 (DONEIEN)DONEIEN 0 (BLOCK)REQMODE 0 (DECLOOPCNT)DECLOOPCNT 0 (IGNORESREQ)IGNORESREQ 0 (ONE)SRCINC 0 (BYTE)SIZE 0 (ONE)DSTINC 0 (ABSOLUTE)SRCMODE 0 (ABSOLUTE)DSTMODE

REQMODE=BLOCK, SRCINC=ONE, SIZE=BYTE, DSTINC=ONE, DSTMODE=ABSOLUTE, BLOCKSIZE=UNIT1, SRCMODE=ABSOLUTE, STRUCTTYPE=TRANSFER

Description

No Description

Fields

STRUCTTYPE

DMA Structure Type

0 (TRANSFER): DMA transfer structure type selected.

1 (SYNCHRONIZE): Synchronization structure type selected.

2 (WRITE): Write immediate value structure type selected.

STRUCTREQ

Structure DMA Transfer Request

XFERCNT

DMA Unit Data Transfer Count

BYTESWAP

Endian Byte Swap

BLOCKSIZE

Block Transfer Size

0 (UNIT1): One unit transfer per arbitration

1 (UNIT2): Two unit transfers per arbitration

2 (UNIT3): Three unit transfers per arbitration

3 (UNIT4): Four unit transfers per arbitration

4 (UNIT6): Six unit transfers per arbitration

5 (UNIT8): Eight unit transfers per arbitration

7 (UNIT16): Sixteen unit transfers per arbitration

9 (UNIT32): 32 unit transfers per arbitration

10 (UNIT64): 64 unit transfers per arbitration

11 (UNIT128): 128 unit transfers per arbitration

12 (UNIT256): 256 unit transfers per arbitration

13 (UNIT512): 512 unit transfers per arbitration

14 (UNIT1024): 1024 unit transfers per arbitration

15 (ALL): Transfer all units as specified by the XFRCNT field

DONEIEN

DMA Operation Done Interrupt Flag Set En

REQMODE

DMA Request Transfer Mode Select

0 (BLOCK): The LDMA transfers one BLOCKSIZE per transfer request.

1 (ALL): One transfer request transfers all units as defined by the XFRCNT field.

DECLOOPCNT

Decrement Loop Count

IGNORESREQ

Ignore Sreq

SRCINC

Source Address Increment Size

0 (ONE): Increment source address by one unit data size after each read

1 (TWO): Increment source address by two unit data sizes after each read

2 (FOUR): Increment source address by four unit data sizes after each read

3 (NONE): Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.

SIZE

Unit Data Transfer Size

0 (BYTE): Each unit transfer is a byte

1 (HALFWORD): Each unit transfer is a half-word

2 (WORD): Each unit transfer is a word

DSTINC

Destination Address Increment Size

0 (ONE): Increment destination address by one unit data size after each write

1 (TWO): Increment destination address by two unit data sizes after each write

2 (FOUR): Increment destination address by four unit data sizes after each write

3 (NONE): Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.

SRCMODE

Source Addressing Mode

0 (ABSOLUTE): The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.

1 (RELATIVE): The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.

DSTMODE

Destination Addressing Mode

0 (ABSOLUTE): The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.

1 (RELATIVE): The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.

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